This invention relates generally to semiconductor metalization system and methods and more particularly to metalization systems having reduced inter-conductor capacitance.
As is known in the art, current method to form electrical conductors (i.e., conducting wires) are categorized into the following methods: A reactive ion etching (RIE) method; and a dual Damascene method. With the RIE method, a dielectric layer 10 is formed over a semiconductor substrate 12, as shown in FIG. 1A. Via holes 14 are etched through selected regions of the dielectric layer 10 using a patterned photoresist mask 16, as shown in FIG. 1B. The mask 16 is removed as shown in FIG. 1C. A metalization layer 18 is deposited over the surface of the etched dielectric layer 12 and through the etched via holes 14, as shown in FIG. 1D. A second photoresist layer 20 is then patterned as shown in FIG. to expose portions of the metalization layer 18 which are to separate the conductors to be patterned into the metalization layer 18. A RIE process is then used to remove the exposed portions of the metalization layer 18 to thereby form the dielectrically isolated conductors 22, as shown in FIG. 1F.
With the dual Damascene method, again a dielectric layer 10 is formed over a semiconductor substrate 12, as shown in FIG. 2A. Via holes 14 are etched through selected portions of the dielectric layer 10 using a patterned photoresist mask 16, as shown in FIG. 2B. The mask 16 is removed, as shown in FIG. 2C. A second photoresist layer 16' is formed over the dielectric layer 10 and is patterned to expose surface portions of the dielectric layer 10 disposed around the periphery 15 of the via holes 14, as shown in FIG. 2D. The exposed surface portions of the dielectric layer 10 are etched to form recesses 141 in the dielectric layer 10 around the upper portions of the via holes 14, as shown in FIG. 2E. A metalization layer 18 is deposited over the surface of the etched dielectric layer 10, portions of the metalization layer passing through the via holes 14, other portions of the metalization layer being disposed in the recesses 14' and still other portions of the metalization layer 18 being disposed on the surface of the dielectric layer 10, as shown in FIG. 2F. The portions of the metalization layer 18 disposed on the upper surface of the dielectric layer 10 are removed by, for example, chemical mechanical polishing (CMP) to thereby form the dielectrically isolated conductors, as shown in FIG. 2G. It is noted that the upper surface portions of the conductors 22' are exposed for connection to other devices or other metalization layers, not shown, which may be formed over the metalization layer 18.
With both of these methods, the capacitance between adjacent conductors 22, 22' is inversely proportional to the distance, d, between such adjacent conductors. Thus, an increase in device density will correspondingly reduce the distance d and increase the capacitance between adjacent conductors. This increase in capacitance results in delay to signals passing through the conductors 22, 22'.